Lock or locked loop circuits, such as phase locked-loop (PLL) and delay locked-loop (DLL) circuitry, are widely used as clock generators for a variety of applications including microprocessors, wireless devices, serial link transceivers, disk drive electronics, and so forth. FIG. 1 illustrates a typical charge pump based PLL circuit 110 that may include phase frequency detector PFD 110, charge pump CP 120, loop filter LPF 130, voltage control oscillator VCO 140, and a divide by M divider 150 and a divide by N divider 152.
The PLL 100 of FIG. 1 has a voltage control oscillator VCO 140 that generates an output clock CKOUT that is frequency locked and phase aligned with an input clock CKIN due to the negative feedback loop. The output clock frequency is defined by the equation CKOUT=CKIN*(N/M), when the PLL 100 is in the lock condition. The inputs chef and ckfb of the phase frequency detector PFD 110 will be phase aligned to each other.
As illustrated in circuit 200 of FIG. 2, a clock tree 220 may be added at the output of the PLL/DLL 210. The output of the clock tree, QK, is required to be phased aligned with CKIN. The input ckfb may be fed back from the QK signal to the PLL/DLL 210 as shown. FIG. 2 is a simplified version of a PLL/DLL with a clock tree where M=1 and N=1.
Next, a known PLL/DLL circuit 300 with a plurality of clock trees 320, 322, 324 is shown in FIG. 3. Since the clock trees 320, 322, 324 are provided at different locations, there will necessarily be skew among the clock trees 320, 322, 324. The clock trees may be designed to minimize the skew between their outputs and the input clock CKIN, but an undesirable amount of skew will still be present. A feedback clock signal, ckfb, is typically derived from one of the clock tree outputs, such as first clock tree output QK_lf in FIG. 3. When the PLL circuit 310 is locked, the input clock CKIN will be phase aligned to the first clock tree output QK_lf. However, since there is skew between first clock tree output QK_lf and second clock tree output QK_rt, the input clock CKIN will not be precisely phase aligned with the second clock tree output QK_rt.
FIG. 4 illustrates clock waveforms of an input clock CKIN, a first clock tree output QK_lf and a second clock tree output QK_rt. FIG. 4 shows a skew between CKIN and QK for a PLL circuit using the second clock tree output QK_rt as a feedback clock.
It should be noted that in FIG. 3, Qk_lf is provided as an input signal for the feedback clock ckfb while Qk_rt is provided as the input signal for the feedback clock ckfb in FIG. 4 in order to illustrate that either of the clock tree outputs Qk_rt, Qk_lf may provide the feedback clock signal.
As set forth below, one or more exemplary aspects of the disclosed circuit and method may overcome such shortcomings and/or otherwise impart innovative aspects by, for example, providing circuitry that reduces skew between an input clock and a plurality of clock tree outputs.